Frontend VLSI

Use “Ctrl+F” to find the topic you are looking for.


There is a hashtag on LinkedIn called “#100daysof RTL” by Abhishek Vashist who shared EDA playground links for each exercise. It is good to follow this to get more hands-on practice with RTL coding. Click here to access the hashtag


SVA cheat sheet by VLSI CLUB


Front-end Useful links by VLSI_FRONT_END


YouTube Channels

VLSI Chaps

  • System Verilog
  • VLSI Job preparations

VLSI for all

  • System Verilog and UVM
  • Digital Electronics
  • Interview Experience and Questions
  • VLSI Projects
  • Protocols
  • CMOS Fabrication
  • General VLSI Awareness

VerilogHDL

  • Verilog HDL
  • Labs with explanation
  • UDP

Adi Teman

  • Digital IC Design
  • Linux and VIM
  • Digital Microelectronics

It is available in Israel language too. Thanks to Divyang Thakkar for sharing this resource

Karthik Vippala

  • Digital Design
  • Advance Digital Design
  • Computer Organization
  • Clock Domain Crossing

Blogs

Some of these resources were curated and shared by VLSIFRONTEND, a community helping front-end learners(telegram link – click here).

VLSI Frontend Docs – curated by Anand Saurabh

https://drive.google.com/drive/folders/1ggW-6DQzkeixILCNPE4e2KTc5AF0f4gL

Cadence Design Systems – Blog

This is the official blog of Cadence Design Systems company.


Synopsys – Blog

This is the official blog of Synopsys company.


Doulos

It contains courses on Verilog, SystemVerilog, SystemC, Perl, Tcl, FPGA etc, Do check their website for more info.


Verification Excellence

  • Verilog
  • SystemVerilog
  • UVM
  • General Verification Domain awareness
  • Github Repo with references – click here
  • Interview Resources

Verification Academy (Siemens)

Mentor Graphics’ Verification Academy is a first of its kind—unlike anything in the industry. Its goals are to provide the skills necessary to mature an organization’s advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details).” – official website


Verification for all

  • Verilog
  • SystemVerilog
  • UVM
  • Protocols
  • SoC Verification
  • Digital Basics

Verilog Pro

  • Verilog
  • SystemVerilog

Verification guide

  • SystemVerilog
  • UVM
  • SystemC
  • Interview Questions
  • Quiz

ChipVerify

  • Verilog
  • SystemVerilog
  • UVM

Testbench

  • Verilog
  • System Verilog
  • OpenVera
  • Specman Tutorials
  • Interview questions

Verilog Codes / VHDL guru Blog Spot

  • Verilog and VHDL tricks, tips and codes

ASIC guru

  • Verilog
  • System Verilog
  • Methodologies (OVM/UVM)
  • Verification Basics
  • Scripting tutorials

Website is not working as of 27 Nov 2021 9 PM IST


FPGA 4 Student

  • Verilog projects
  • FPGA Tutorial
  • FPGA projects
  • VHDL projects

VLSI Pro – Front end

  • Verification
    • Assertion based verification
    • Equivalence Checking
    • Simulation Based

VLSI 4 freshers

  • Digital Design
  • FPGA
  • Verilog
  • Interview Questions

ASIC world

  • Digital
  • Verilog
  • SystemVerilog
  • Specman
  • SystemC
  • VERA
  • PSL
  • VHDL
  • Scripting

Quick Silicon

There are two sections in this link – learn and compete. Under compete section, it has various hackathons. Under learn section, it covers learning modules on trending technologies. At present, RISC-V and Verilog module-to-module are the active tracks.

Thanks to Rahul.B for recommending this website.

Website is not working as of 4th Nov 2022


Semicon Referrals Blog

This blog mainly covers UVM Basics explaining its advantages, UVM Class Hierarchy and Testbench Structure in general. It also covers Industry related news in this domain.


Formal Verification blogs

This blog is written by Ashish Darbari who talks about formal verification concepts.


Digital Design – Expert Advice

This blog is written by Rahul Jain.

  • Digital Design
  • Synthesis
  • STA
  • Lint
  • CDC
  • Protocols – I2C, UART, PCIe, SPI
  • Interview materials
  • Scripting
  • Verilog Tutorials
  • Educational / Academic projects with codes
  • General VLSI industry topics and Suggestions

The Art of Verification

  • System Verilog
  • UVM
  • Functional Coverage
  • Assertions
  • Interview Questions

VLSI Universe

  • VLSI
  • Verilog
  • OS
  • Interview Questions

VLSI Verify

  • Verilog
  • System Verilog
  • UVM

Project evlsi

  • Digital basics
  • Verilog
  • Puzzles

Required an account to access content
Website is not working as of 4th Nov 2022


Digital Design – Expert Advice

  • VLSI Projects
  • CDC
  • Protocols
  • Design Basics
  • STA and Timing constraints
  • RTL Code
  • Low power related concepts
  • VLSI Interview Questions
  • PCIe